A logarithmic amplifier is a device that provides an output signal that will increment by a fixed amount each time the input signal increases by some factor. For example, a log amplifier may be designed to increment its output signal in response to a tripling or quadrupling of the input signal.
Early developments in logarithmic amplifiers came from the need to create a form of automatic gain control with high dynamic range in receivers for radar and electronic warfare. In these applications, the received signal power can vary by many orders of magnitude due to obstructions and reflections in the transmitting path. Logarithmic amplifiers are used to compress this large signal range into a smaller range that is more easily monitored on an electronic display or more easily captured with an analog-to-digital converter. Furthermore, a log amplifier may be used wherever the need for logarithmic arithmetic arises in instrumentation and signal processing in general.
Logarithmic amplifiers may also be used in fiber-optic receivers for gain control. The detected power in a fiber-optic receiver can vary due to bias point drift in both the transmitting laser and the receiver photodiode. Logarithmic amplifiers have been used to compress the high range of power levels provided by the photodiode. The advantage is to ease the task of the decision circuitry within the receiver and to protect it from optical overload.
Logarithmic converters may also be used in optical transmitters to aid in the task of performing single-sideband modulation of optical signals. An optical modulation system 10 that uses a logarithmic converter is shown in FIG. 1. An electrical information signal 100 is input to an optical amplitude modulator 104, and so the information signal amplitude-modulates the optical signal 102. As well, the signal is input to a logarithmic converter 106 serially coupled to a Hilbert transformer 108. Using an optical phase modulator 110, the output of the Hilbert transformer is used to phase-modulate the output of the optical amplitude modulator. The output of the phase modulator is an optical single-sideband signal 112. This scheme is particularly suited to high-data rate, baseband digital signals. The modulator is further described in U.S. Pat. No. 5,949,926.
There are two general categories of logarithmic converters; single stage converters and piecewise-approximate converters. Single stage converters, such as those that exploit the exponential voltage-to-current relation of PN junctions in bipolar transistors and diodes, provide efficient logarithmic conversion in low frequency applications. However, the present invention is concerned with high frequency operation and so only converters providing a piecewise-approximation to a logarithm are considered.
Piecewise-approximate logarithmic amplifiers may be subdivided into those that operate in a xe2x80x98truexe2x80x99 mode (also called xe2x80x98basebandxe2x80x99 or xe2x80x98videoxe2x80x99), or a demodulating mode, or those that may operate in both modes. Demodulating logarithmic amplifiers provide the logarithm of the envelope of the input signal, as opposed to the logarithm of the entire signal provided by true logarithmic amplifiers. The present invention is primarily concerned with improving logarithmic amplifiers operating in the true mode, and so the demodulating ability of logarithmic amplifiers will not be discussed further here.
A progressive-compression logarithmic amplifier 20 is shown in FIG. 2. The signal path includes serially coupled amplifiers 204, with the output voltage of each amplifier coupled to a limiting transconductance element 206. The unamplified input signal is coupled to limiting transconductance element 206A that has a higher gain than elements 206. FIG. 3 parts (a) and (b) show the input-output characteristic of transconductance elements 206 and 206A respectively. A current bus 208 sums the output currents of all such elements to provide a system output current that is logarithmically related to the input signal 202. Typically the current bus is terminated by a resistive element 210 to provide an output voltage 212. Since the currents are summed in parallel, amplifier 20 belongs to the class of parallel summation logarithmic amplifiers.
In the progressive-compression amplifier in FIG. 2, relatively small input signals are simply amplified, whereas larger signals will cause the transconductance elements in each path to limit, starting with the last path and progressing toward the first path. FIG. 4 shows the DC response 402 of amplifier 20, where the transfer function of a four-path progressive-compression amplifier is shown. The amplifier response approximates a straight line in FIG. 4 because it is plotted on a semi-logarithmic axis. In order to reduce the error between the cusps of the approximation, more stages with smaller gains must be cascaded.
Progressive-compression amplifiers take advantage of multiple cascaded amplifiers to provide high gain. High gain directly translates into high dynamic range, because the logarithmic dynamic range extends from the point where the gain is highest to where the gain compresses to zero. In addition, progressive-compression amplifiers are easy to design since all of the cascaded stages are the same or similar. They also exhibit high tolerance to manufacturing process and temperature variations since these factors are likely to effect the gain of amplifiers 204 equally, which will simply shift or scale the logarithmic response without significantly distorting its logarithmic characteristics.
A limit on the frequency range of the progressive-compression amplifier may be seen by considering that the component amplifiers 204 each have finite bandwidth. If a single pole dominates the frequency response of these amplifiers, then the phase response of each amplifier will be close to xe2x88x9245 degrees near the pole frequency. The input signal 202 in FIG. 2 will pass through element 206A to the current bus with little phase shift, and this signal must be added in parallel with the output of the last serially-coupled amplifier 204 which will have significant phase shift from having passed through several amplifiers. Hence, if out-of-phase addition is to be avoided, either the amplifier must be operated well below its frequency limit, or the signals with little phase delay must have phase delay added to them prior to summation.
Another type of serially coupled logarithmic converter that exhibits better internal phase matching is the series linear-limit logarithmic amplifier 50 shown in FIG. 5, also known as the twin-gain stage logarithmic amplifier from A. Woroncow and J. Croney, xe2x80x9cA True I.F. Logarithmic Amplifier using Twin-Gain Stagesxe2x80x9d, The Radio and Electronic Engineer, September 1966, pp. 149-155. A number of identical stages 508 consisting of a limiting amplifier 506 in parallel with a buffering network 502 are cascaded. An input signal 504 that is relatively small will simply be amplified by all stages, while larger signals will cause the limiting amplifiers 506 to limit, starting with the last stage and progressing toward the input. The DC transfer function 404 of a logarithmic amplifier with three twin-gain stages is shown in FIG. 4. It may be seen that the response of the twin-gain stage amplifier is similar to that of the progressive-compression amplifier except beyond point 406. Point 406 approximately indicates the highest power levels handled by the logarithmic amplifier. Correct operation of the twin-gain stage amplifier requires that all of the buffering amplifiers 502 continue to pass the signal up to the input voltage indicated by point 406. The effect of this requirement on the bandwidth of the twin-gain stage 508 may be shown using the schematic diagram of one of the twin-gain stages in FIG. 6.
FIG. 6 shows two parallel differential-pair amplifiers in bipolar integrated circuit technology with shared collector resistance 602. The high-gain limiting amplifier includes transistors 606 and the low gain buffering amplifier includes transistors 604 and resistors 608 which are required to set the gain of the buffer amplifier. Referring to FIG. 5, it is required that the buffer amplifier 502 in the last stage continue to pass the signal, even after the amplifiers 506 in all previous stages limit and contribute a voltage VL. The signal passed through the buffering amplifier in the last stage is thus equal to (Nxe2x88x921)VL. In the schematic diagram in FIG. 6, the value VL is equal to the product of Ihigh (at 612) and Rc. The limiting value of the buffering amplifier, equal to the product of Ilow (at 610) and Rc, must be at least Nxe2x88x921 times higher than VL. For this reason, Ilow must be at least Nxe2x88x921 times higher than Ihigh. However, Ihigh is relatively high in order to achieve the required gain, so Ilow will be quite high, requiring the use of large, high power devices with high parasitic capacitance. This capacitance will load the high gain stage and lower its bandwidth. One way to ease the output voltage swing requirements on the buffer amplifier is to lower its gain below unity, so that more input power is required in order for it to limit. However, the buffer amplifiers will still have some parasitic capacitance associated with them and this capacitance will still load the high gain amplifier in parallel and lower the bandwidth of the twin-gain stage.
Parallel amplification logarithmic converters overcome problems with internal delay matching and buffering requirements at the cost of decreased logarithmic dynamic range. FIG. 7 shows a parallel logarithmic amplifier 70. The amplifier consists of a single input coupled to a number of parallel voltage amplifiers 702A-N with gains as indicated. The output of each parallel amplifier is limited to the voltage range + xe2x88x92VL by limiters 704. Since the outputs of the limiters 704 are summed at 706 in parallel just as in amplifier 20, amplifier 70 also belongs to the class of parallel summation logarithmic amplifiers. The gains of the parallel amplifiers 702 may be uniformly scaled by an arbitrary factor, which may reduce the gain of some paths below unity so that attenuators are used in place of amplifiers. The use of attenuators is undesirable in many applications though, since it increases the required input voltage needed to saturate the limiters 704 or requires limiters with lower corner voltages for a given drive power at the logarithmic amplifier input. As well, a large amount of attenuation increases the noise figure of the converter significantly.
Although parallel amplification logarithmic converters exhibit internal delay matching and low group delay distortion overall, they have distinct disadvantages. Since the parallel amplifiers have significantly different gains, it is more difficult than with serially coupled structures to achieve a logarithmic response that is highly tolerant of process variation. In addition, the parallel architecture is at a disadvantage in high-dynamic range applications since it does not exploit the high gain offered by cascaded amplifier structures.
What is needed is a logarithmic amplifier that attains relatively high gain, bandwidth, and efficiency; and internally matched phase and group delay, all with high tolerance to process variation.
Accordingly, it is one object of the present invention to provide a logarithmic amplifier with matched group delay amongst its internal paths.
It is another object of the invention to provide a logarithmic amplifier with high bandwidth.
Still another object of the invention is to provide a logarithmic amplifier with high dynamic range.
A further object of the invention is to provide a logarithmic amplifier that occupies little area when fabricated on an integrated circuit.
A still further object of the invention is to provide a logarithmic amplifier with low power consumption.
A still further object of the invention is to provide a logarithmic amplifier with high tolerance to process and temperature variation.
A still further object of the invention is to provide a low-noise logarithmic amplifier.
Therefore according to a first aspect of the invention, there is provided a piecewise-approximate logarithmic amplifier. In one embodiment, the amplifier has of a number of different amplification paths, called the gain section, with a summing/limiting circuit that provides the logarithmic output. The highest gain path consists of a cascade of N high gain amplifiers, where N is an integer greater than one. In a further aspect of the invention, there are at least N+2 amplification paths, and these paths share amplifiers as much as possible. The output of each path passes through a circuit that limits the output signal at a certain level, with the limiting level for each path being preferably the same except the limiting level for the lowest gain path, which may be higher. After being limited, the path outputs are summed to form the logarithmic output.
The gains of all paths may be chosen using a unique design procedure, wherein it is shown that these gains result in an exact logarithmic relationship at fixed points on the characteristic between the logarithmic amplifier""s input and output signals.
A means is provided for designing the group and phase delay of each path in parallel summation logarithmic amplifiers to be nearly the same. One preferred delay method involves the use of delay amplifiers where the delay is set using capacitive elements. This delay method is used in the novel branch logarithmic amplifier described above, and may also be used to equalize the delay of the signals in a progressive-compression logarithmic amplifier.
The novel idea of using parallel feedback amplifiers (PFAs) as a building block in logarithmic amplifiers is described. PFAs are linear amplifiers that may be designed to have significantly different gains but similar phase characteristics. Hence, if these amplifiers are used as the logarithmic amplifier building block, then delay tuning may be accomplished using only the parasitic capacitances inherent in transistors. PFAs also have a higher bandwidth than standard differential pairs. However, since PFAs are very similar to differential pairs, then they may be used in place of differential pairs in both parallel summation logarithmic amplifiers and in the series linear-limit logarithmic amplifier.
The preferred embodiment of the logarithmic amplifier is DC coupled and uses fully balanced differential-pair amplifiers. Some optional circuits for reducing DC offsets are described. These circuits may be placed in negative feedback around the high-gain components of the logarithmic amplifier, and may be switched on or off.
The branch logarithmic amplifier and a matched delay progressive-compression amplifier have extremely high bandwidth and low group delay distortion. Accordingly, one application of these structures is in the single-sideband optical modulator shown in FIG. 1.
These and other aspects of the invention are described in the detailed description of the invention and claimed in the claims that follow.